The present disclosures relate to semiconductor memory devices, and more particularly, to a self-aligned split gate nanocrystal memory cell and method for making the same.
In a prior method of forming a split-gate nanocrystal memory cell device, the method uses a non-self aligned approach to pattern the control and select gates of the device. Since the formation of the control and select gates relies on more than one mask, registration errors occurring during the photolithography steps in the manufacture thereof result in significant variation in the gate length of the device gates. The registration errors and resulting variations in gate length of the device gates are highly undesirable.
Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art as discussed above.
The use of the same reference symbols in different drawings indicates similar or identical items. Skilled artisans will also appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.